The present invention relates to a sample-and-hold circuit for sampling and holding the output signals of an A/D converter used in communications systems, audio systems, video systems and the like.
Such a sample-and-hold circuit is disclosed in Rudy J. Van de Plassche, et al. A Monolithic High-Speed Sample-and-Hold Amplifier for Digital Audio in IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 6, December 1983, p. 717 (FIG. 1). FIG. 1 shows the structure of this circuit. In this sample-and-hold circuit, an input signal V.sub.IN is supplied to the non-inverting input terminal (+) of operational amplifier 11 through resistor R1 and switch S1. The output of operational amplifier 11 is fed back to the inverting input terminal (-) of amplifier 11. It is also supplied to the inverting input terminal (-) of operational amplifier 12 through switch S3. The non-inverting input terminal (+) of operational amplifier 12 is grounded. The output of amplifier 12 is fed back to the inverting input terminal (-) of amplifier 12 through holding capacitor C.sub.H. It is also supplied to node N1 of resistor R1 and switch S2 through resistor R2. Switch S2 is connected between node N1 and the ground. Switches S1, S2 and S3 are selectively turned on and off, thereby controlling the operation of sampling and holding input signal V.sub.IN and thus obtaining output signal V.sub.OUT at the output terminal of operational amplifier 12.
In the sample-and-hold circuit (SHC) of FIG. 1, an imaginary short-circuit occurs when switches S1 and S3 are simultaneously turned on. Potentials V1, V2 and V3 of node N1, node N2 (i.e., the output terminal of amplifier 11) and node N3 (i.e., the non-inverting input terminal of amplifier 12) thereby fall to the ground level. As a result, output signal V.sub.OUT becomes -V.sub.IN. In other words, an inverse of input signal V.sub.IN is obtained at the output terminal of operational amplifier 12. When switches S1 and S3 are turned off and switch S2 is turned on, holding capacitor C.sub.H maintains the output of operational amplifier 12 at a level attained in the previous sampling cycle. Since switch S2 is on, potential V1 of node N1 is reliably held at the ground level.
It will now be explained how sample-and-hold circuit SHC shown in FIG. 1 functions to sample and hold the output of D/A converter 13 when circuit SHC is coupled to D/A converter 13 as is illustrated in FIG. 2.
When switch S4 connected between D/A converter 13 and sample-and-hold circuit SHC is turned on, thus coupling the output terminal of D/A converter 13 to the input terminal of sample-and-hold circuit SHC, input signal V.sub.IN of circuit SHC has the following value: EQU V.sub.IN =VDAC.multidot.R/(Z+R)
where Z is the output impedance of D/A converter 13, V.sub.DAC is the output which D/A converter 13 produces when the output terminal of the converter is opened by turing off switch S4, and R is the input resistance of sample-and-hold circuit SHC.
Obviously, the higher the impedance (Z), the more the input signal (V.sub.IN) attenuates. The condition of Z&lt;&lt;R is therefore required. To satisfy this requirement, output impedance Z of D/A converter 13 must be lowered, or input resistance R of sample-and-hold circuit SHC must be raised.